1. Field of the Invention
This invention relates to a device of a liquid crystal display, and more particularly to a thin film transistor substrate for a display device and a fabricating method thereof.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of a liquid crystal using an electric field to thereby display a picture. The LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal display panel. The liquid crystal display panel includes a thin film transistor substrate and a color filter substrate that are opposed to each other, a liquid crystal injected between the two substrates, and a spacer for keeping a cell gap between the two substrates.
The thin film transistor substrate includes gate lines and data lines that cross each other. Liquid crystal cells are defined between adjacent pairs of gate lines and data lines. Thin film transistors are respectively formed adjacent to crossings of the gate lines and the data lines. The thin film transistor are switching devices connected to the data lines and gate lines. Pixel electrodes are formed in each liquid crystal cell and connected to the thin film transistor. An alignment film is coated onto the liquid crystal cells of thin film transistor substrate. The gate lines and the data lines receive signals from the driving circuits via pad portions on each of the lines. The thin film transistor applies a pixel signal to the pixel electrode from the data line in response to a scanning signal on the gate line.
The color filter substrate includes color filters formed in each liquid crystal cell. A black matrix on the color filter substrate divides the color filters. Common electrodes for commonly applying reference voltages to the liquid crystal cells are formed on the color filters. An alignment film is coated on the common electrode.
The liquid crystal display panel is assembled by joining the thin film array substrate and the color filter substrate together. Then, liquid crystal is injected between the thin film array substrate and the color filter substrate followed by a sealing of the hole in which the liquid crystal was injected. In manufacturing such a liquid crystal display, the process for forming the thin film transistor substrate is complicated and is a major factor in the manufacturing cost of the liquid crystal display panel. The semiconductor processes for forming the thin film transistor is expensive because it needs a plurality of masking processes. One mask process includes a lot of processes, such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes, etc. In order to address the cost of the semiconductor processes, a thin film transistor substrate has been developed that can be produced with a reduced number of mask processes. Recently, a four-round mask process, which has one less mask process than the existing standard five-round mask process, has been developed.
FIG. 1 is a plan view illustrating a thin film transistor substrate fabricated by a four-round mask process, and FIG. 2 is a cross-section view of the thin film transistor substrate taken along the I–I′ line in FIG. 1. Referring to FIG. 1 and FIG. 2, the thin film transistor substrate includes a gate line 2 and a data line 4 provided on a lower substrate 42 in such a manner as to cross each other with a gate insulating film 44 therebetween. A thin film transistor 6 is provided adjacent to each crossing. A pixel electrode 18 connected to the thin film transistor 6 is provided in a cell area defined by the gate line 2 and the data line 4. Further, the thin film transistor substrate includes a storage capacitor 20 provided where the pixel electrode 18 overlaps the gate line 2 of another cell area. A gate pad portion 26 is connected to the gate line 2 and a data pad portion 34 is connected to the data line 4.
The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to the pixel electrode 18. An active layer 14 overlaps the gate electrode 8 and has a channel between the source electrode 10 and the drain electrode 12. The active layer 14 also overlaps with the data line 4, a lower data pad electrode 36 and an upper storage electrode 22, as shown in FIG. 2. On the active layer 14, an ohmic contact layer 48 for making an ohmic contact with the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 36 and the upper storage electrode 22 is further provided. The thin film transistor 6 provides a pixel signal to the pixel electrode 18 from the data line 4 in response to a scanning signal applied to the gate line 2.
The pixel electrode 18 is connected, via a first contact hole 16 passing through a protective film 50, to the drain electrode 12 of the thin film transistor 6. A potential difference between the common electrode provided at an upper substrate (not shown) and the pixel electrode is generated when a pixel signal is applied to the pixel electrode. This potential difference rotates liquid crystal positioned between the thin film transistor substrate and the upper substrate due to dielectric anisotropy of the liquid crystal and light from a light source (not shown) can transmit therethrough.
The storage capacitor 20 consists of an upper storage electrode 22 overlapping the gate line 2 of another cell area with a gate insulating film 44, the active layer 14 and the ohmic contact layer 48 therebetween. The pixel electrode 18 overlaps the upper storage electrode 22 with the protective film 50 therebetween and is connected via a second contact hole 24 in the protective film 50. The storage capacitor 20 allows a pixel signal charged in the pixel electrode 18 to be stably maintained until the next pixel signal.
The gate line 2 is connected, via the gate pad portion 26, to a gate driver (not shown). The gate pad portion 26 consists of a lower gate pad electrode 28 extending from the gate line 2, and an upper gate pad electrode 32 connected, via a third contact hole 30 passing through the gate insulating film 44 and the protective film 50, to the lower gate pad electrode 28. The data line 4 is connected, via the data pad portion 34, to the data driver (not shown). The data pad portion 34 consists of a lower data pad electrode 36 extended from the data line 4, and an upper data pad electrode 40 connected, via a fourth contact hole 38 passing through the protective film 50, to the lower data pad electrode 36.
Hereinafter, a method of fabricating the thin film transistor substrate having the above-mentioned structure adopting the four-round mask process will be described in detail with reference to FIG. 3A to FIG. 3D. Referring to FIG. 3A, gate metal patterns including the gate line 2, the gate electrode 8 and the lower gate pad electrode 28 are provided on the lower substrate 42 by the first mask process.
First, a gate metal layer is formed on the lower substrate 42 by a deposition technique, such as sputtering. Then, the gate metal layer is patterned by photolithography. An etching process using a first mask is then performed to thereby form gate metal patterns including the gate line 2, the gate electrode 8 and the lower gate pad electrode 28. The gate metal layer can be a single-layer or double-layer structure of chrome (Cr), molybdenum (Mo) or an aluminum group metal, etc.
Referring to FIG. 3B, the gate insulating film 44 is coated onto the lower substrate 42 provided with the gate metal patterns. Further, a semiconductor pattern including the active layer 48 is provided on the gate insulating film 44 using a second mask. In addition, the ohmic contact layer 48 and source/drain metal patterns including the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 36 and the upper storage electrode 22 are also provided in the second mask process.
More specifically, the gate insulating film 44, an amorphous silicon layer, a n+ amorphous silicon layer and a source/drain metal layer are sequentially provided on the lower substrate 42 provided with the gate metal patterns by deposition techniques, such as the plasma enhanced chemical vapor deposition (PECVD) and the sputtering, etc. Herein, the gate insulating film 44 is formed from an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiOx). The source/drain metal is selected from molybdenum (Mo), titanium (Ti), tantalum (Ta) or a molybdenum alloy, etc.
Then, a photo-resist pattern is formed on the source/drain metal layer by photolithography using the second mask. In this case, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used as a second mask, thereby allowing a photo-resist pattern of the channel portion to have a lower height than other source/drain pattern portion.
Subsequently, the source/drain metal layer is patterned by a wet etching process using the photo-resist pattern to thereby provide the source/drain metal patterns including the data line 4, the source electrode 10, the drain electrode 12 being integral to the source electrode 10 and the upper storage electrode 22. Next, the n+ amorphous silicon layer and the amorphous silicon layer are patterned at the same time by a dry etching process using the same photo-resist pattern to thereby provide the ohmic contact layer 48 and the active layer 14.
The photo-resist pattern having a relatively low height is removed from the channel portion by the ashing process and thereafter the source/drain metal pattern and the ohmic contact layer 48 of the channel portion are etched by the dry etching process. Thus, the active layer 14 of the channel portion is exposed to disconnect the source electrode 10 from the drain electrode 12. Then, the photo-resist pattern left on the source/drain metal pattern group is removed by the stripping process.
Referring to FIG. 3C, the protective film 50 including the first to fourth contact holes 16, 24, 30 and 38 are formed on the gate insulating film 44 provided with the source/drain metal patterns. More specifically, the protective film 50 is entirely formed on the gate insulating film 44 provided with the source/drain metal patterns by a deposition technique, such as the plasma enhanced chemical vapor deposition (PECVD). Then, the protective film 50 is patterned by photolithography and the etching process using a third mask to thereby define the first to fourth contact holes 16, 24, 30 and 38. The first contact hole 16 is formed to pass through the protective film 50 and expose the drain electrode 12, whereas the second contact hole 24 is formed to pass through the protective film 50 and expose the upper storage electrode 22. The third contact hole 30 is formed to pass through the protective film 50 and the gate insulating film 44 and expose the lower gate pad electrode 28. The fourth contact hole 38 is formed to pass through the protective film 50 and expose the upper data pad electrode 36.
The protective film 50 is made from an inorganic insulating material identical to the gate insulating film 44, or an organic insulating material, such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.
Referring to FIG. 3D, transparent conductive film patterns including the pixel electrode 18, the upper gate pad electrode 32 and the upper data pad electrode 40 are provided on the protective film 50 by the fourth mask process.
A transparent conductive film is entirely deposited onto the protective film 50 by a deposition technique such as the sputtering, etc. Then, the transparent conductive film is patterned by the photolithography and the etching process using a fourth mask to thereby provide the transparent conductive film patterns including the pixel electrode 18, the upper gate pad electrode 32 and the upper data pad electrode 40. The pixel electrode 18 is electrically connected, via the first contact hole 16, to the drain electrode 12 while being electrically connected, via the second contact hole 24, to the upper storage electrode 22. The upper gate pad electrode 32 is electrically connected, via the third contact hole 30, to the lower gate pad electrode 28. The upper data pad electrode 40 is electrically connected, via the fourth contact hole 38, to the lower data pad electrode 36. Herein, the transparent conductive film is formed from indium-tin-oxide (ITO), tin-oxide (TO) or indium-zinc-oxide (IZO).
As described above, the related art thin film transistor substrate and the fabricating method thereof is a four-mask process, which reduces the number of fabricating processes and hence reducing manufacturing cost in proportion to the reduced number of fabricating processes in comparison with those used in the five-mask process. However, the four-round mask process is still a complicated and expensive fabricating process. Thus, there is still a need to simplify the fabricating process and to further reduce the manufacturing cost.